The role of interfaces and defects in controlling the properties of InGaAs based MOS devices

David Wang Auditorium, 3rd floor Dalia Maydan Bldg.
Roy Winter

Roy Winter, PhD candidate
Department of Material Science and Engineering, Technion

The continuous scaling of microelectronic devices demands integration of new materials for future devices. InGaAs is a leading candidate to serve as the channel material of future transistors due to its high carrier mobility with respect to Si. However, replacing Si with InGaAs leads to new
challenges, stemming from a lower interface quality. The experience from Si Metal-Oxide_Semiconductor (MOS) stacks research has established the conclusion that there is a tight connection and complex interaction between all of the gate stack components, emphasizing the importance of studying the properties of the gate stack as a whole.

The objective of this research was to determine the role of interfaces and defects in controlling the properties of MOS devices consisting of a metal electrode, a high-k dielectric, and InGaAs as a high-mobility substrate. In particular interest was the effect of metallization on the
electrical properties of these devices, and their correlation with the composition and band structure of the high-K/semiconductor interface.We have used electrical characterization methods combined with HR-TEM, ToF-SIMS, and XPS in order to achieve the research goals.

At the first stage, we have developed a new method for determining the flat-band voltage in high mobility semiconductors, insensitive to the high density of interface traps typical of these materials.

By using this new method, we have correlated Fermi level pinning with the materials constituting the gate stack, the metal deposition methods, and various processing steps such as postoxide and post-metal deposition annealing. We have examined the effects of the type of the gate
metal used and its deposition method on the presence of point defects in the gate stacks and on the chemical stability of key interfaces.

Finally, we have demonstrated reduction of interface trap density by oxides scavenging using a Ti thin layer. The scavenging of InGaAs native oxides in Ti/High-k/InGaAs gate stack was investigated using electrical measurements and synchrotron XPS analysis.

PhD advisor: Prof. Moshe Eizenberg